Model simulation provides a mechanism by which the design of a component (e.g., the design of a hardware chip) can be tested prior to building the component. This testing is to ensure that the component, once built, will meet the desired specifications of the component. The component is tested by creating a model of the component and simulating the model. There are various types of model simulation, including event simulation and cycle simulation. Event simulation takes into account delays within the component (e.g., hardware delays), whereas cycle simulation ignores such delays.
Components, such as logic chips, to be modeled are being developed with ever increasing density and functionality. In fact, the state of the art is evolving to the point where chip capabilities are being characterized as System on Chip (SoC). This increased amount of functionality requires equally proportional improvements in the simulation methodologies used to ensure the proper operation of the components prior to their manufacture. An evolving category of simulation methodologies used to address this concern is distributed event simulation. In distributed event simulation, the horsepower of a set of independent workstations or processors is harnessed to tackle a large or complex chip model. Specifically, the simulation effort is distributed across a set of processors.
For proper simulation of a model across the set of processors, a global simulation time (GST) is employed to control the progression of the simulation. Each processor performs the simulation up to the GST time, and then, waits for a further directive. During the simulation to that time, complex management associated with the GST is needed to ensure that data is exchanged between the processors accurately and coherently.
Different management techniques have been used in the past to manage the GST, including optimistic prediction and conservative advancement of the GST. However, both techniques have proven inadequate for distributed event simulation of complex models, such as dense chips. In particular, as the densities of the chips have increased and as simulation of the dense chips has progressed to distributed simulation, in which several clocks are typically communicating across a network on asynchronous boundaries, the management associated with the GST has become very complex. This complexity is further exacerbated by the use of actual delays present in event simulation.
Therefore, a need exists for a capability that simplifies the management associated with global simulation time. In particular, a need exists for a capability that facilitates simulation of models in a distributed environment. A yet further need exists for a capability that facilitates simulation of models via distributed event simulation.